The present invention relates to a voltage detecting circuit, and more particularly, to a circuit for detecting a level of a programming voltage VPP in an active power down mode of a semiconductor memory device.
A synchronous dynamic random access memory (SDRAM) has various operation modes. One operation mode is an active power down mode for reducing power consumption which requires the reduction of current consumed in a chip.
FIG. 1 is a timing diagram of the signals in an active power down mode, where CK represents a system clock and CKE represents a clock enable signal. When CKE is "High", and thus active, normal memory operations are performed. However, when CKE is "Low," even though the CK is applied from the outside, the clock is not propagated in the semiconductor chip. As a result, normal memory operations cannot be performed.
When the semiconductor memory chip is set to the active power down mode, in which most of operations of the chip are halted, the current consumption in the semiconductor chip is primarily due to internal DC power driving circuits. Among these internal circuits is a circuit for detecting a programming voltage VPP which is typically at a higher voltage level than that of the external power supply VCC. /RAS and /CS represent a row address strobe signal and a chip selection signal, respectively, which are externally applied to the chip. WL and BL represent a wordline and a bitline, respectively, and PAPD represents a mode control signal based on the clock enable signal (CKE).
FIG. 2 is a conventional voltage detecting circuit, which includes a pull-up portion 200, a pull-down portion 201, a switching transistor 202 and a driving portion 203. The pull-up portion 200 includes 2 NMOS transistors 211 and 212 gated by the boosted programming voltage VPP. The pull-down portion 201 includes NMOS transistors 221, 222 and 223 gated by power supply voltage VCC. The driving portion 203 includes inverters 215, 216 and 217. PR, which is a signal based on the /RAS signal, is applied to a gate of the switching transistor 202. Consequently, when the PR signal is "High," the switching transistor 202 is turned-on and the logic state of the driving portion 203 varies according to the level of the boosted voltage VPP applied to the gates of NMOS transistors 211 and 212 of pull-up portion 200. However, this conventional voltage detecting circuit has a single current path regardless of the operation mode of the semiconductor memory chip. High levels of current are required to obtain rapid operation of the voltage detecting circuit during normal operation. As a result, the circuit consumes an unnecessarily large amount of power during active power down mode.